Processors: Structure, Performance and Types | OCR A-Level Computer Science (H446)

Processors: Structure, Performance and Types

91 questions
7 subtopics
Component 01: Computer systems
Component 01

Processors: Structure, Performance and Types is examined on component 01 of OCR Computer Science, Computer systems.

91 recall questions across 7 subtopics.

Sample questions from Processors: Structure, Performance and Types

Answer each one closed book first, then open the answer.

Inside the CPU: ALU, control unit, registers and buses

What is held in the current instruction register, and what two parts does it split into?

Show the answer
The CIR holds the instruction currently being decoded and executed, copied there from the MDR at the end of the fetch. The control unit splits it into the opcode, which says what operation to perform, and the operand, which says what to perform it on: a value, a register, or a memory address.
Inside the CPU: ALU, control unit, registers and buses

What travels on the control bus?

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Control and timing signals rather than data. Typical signals are read, write, the clock pulse used to synchronise components, memory request, interrupt request, bus request and bus grant, and reset. It is bidirectional, because devices send signals back to the processor, an interrupt request being the obvious example.
The fetch-decode-execute cycle

Which register tells you what the processor is doing right now, and which tells you what it is about to do?

Show the answer
The current instruction register holds the instruction being decoded or executed at this moment. The program counter holds the address of the instruction that will be fetched next.
What makes a CPU fast: clock speed, cores and cache

A processor runs at 2.5 GHz. How long is one clock cycle?

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One divided by 2,500,000,000 seconds, which is 0.4 nanoseconds. A useful check: at 1 GHz a cycle is 1 nanosecond, so at two and a half times that speed a cycle is two fifths of a nanosecond.
Von Neumann, Harvard and contemporary architecture

What defines von Neumann architecture?

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A single memory that holds both the program instructions and the data, addressed in exactly the same way, reached through one shared set of buses, with a single control unit fetching and executing one instruction at a time. This is the stored program concept: the program lives in the same memory as the data it works on.
CISC and RISC

What does RISC stand for, and how does its design idea differ?

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Reduced Instruction Set Computer. It provides a small set of simple instructions, each doing one straightforward thing and designed to complete in a single clock cycle. Anything complicated must be built up from several of these, so the complexity moves out of the hardware and into the compiler and the software.
GPUs, multicore and parallel systems

What is a GPU?

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A graphics processing unit: a specialised processor containing hundreds or thousands of small, simple cores designed to perform the same arithmetic operation on very many data items simultaneously, supported by very high memory bandwidth. It was developed to render graphics but is now used for any work of a similar shape.

The 7 subtopics

One subtopic is one session. Work down the list.

Subtopic	What it covers	Questions
Inside the CPU: ALU, control unit, registers and buses	Recall questions on the arithmetic and logic unit, the control unit, the program counter, MAR, MDR, CIR and accumulator, the address, data and control buses, how bus width sets addressable memory and transfer size, and how assembly language relates to the registers.	20
The fetch-decode-execute cycle	Recall questions on the fetch, decode and execute stages, how each register changes during a store, add or jump instruction, conditional and unconditional jumps, which bus carries the instruction, and why the program counter is incremented during the fetch.	13
What makes a CPU fast: clock speed, cores and cache	Recall questions on clock speed and cycle time, why doubling clock speed or adding cores does not double performance, cache hits and misses, L1, L2 and L3 cache, heat, and how clock speed, cores and cache interact.	16
Pipelining	Recall questions on pipelining in a processor, throughput once the pipeline is full, counting clock cycles with and without pipelining, jumps and branch prediction, data dependencies that stall a pipeline, and why RISC pipelines well.	8
Von Neumann, Harvard and contemporary architecture	Recall questions on von Neumann architecture and its bottleneck, Harvard architecture, where each is used, modified Harvard architecture, the features of contemporary processors, and why Harvard does not make von Neumann obsolete.	10
CISC and RISC	Recall questions on CISC and RISC design ideas, instruction length and cycles per instruction, register use and load and store, the burden on the compiler, program length, power use, pipelining, and the typical uses of each.	12
GPUs, multicore and parallel systems	Recall questions on GPUs and why graphics suits massively parallel cores, non-graphics uses of GPUs, when a GPU is the wrong choice, multicore and parallel systems, problems that parallelise, shared data, and why manufacturers added cores.	12

Processors: Structure, Performance and Types is 91 of the 1,549 questions in the guide.Get the guide, £9

How the guide is worked

Answering a question from memory stores it far better than reading the answer again. The guide runs that as a fixed procedure on one subtopic at a time, about twenty minutes a session.

Step 1 · Closed book
Cover the answers. Work through one subtopic and write down what you can. Leave blanks where you have nothing.
Step 2 · Open book
Go back to the top. Read each printed answer and write it out in full, including the ones you had right.
Step 3 · Closed book again
Same questions, same order, from memory. The gap between pass one and pass three is the session result.

Read the full method, the return schedule and the research behind it.